Analytical and Speedup Models for Performance Evaluation of a Generic Reconfigurable Coprocessor (RC) Architecture

New analytical and the speedup models for evaluating the performance of a generic reconfigurable coprocessor (RC) system are presented. We present a generic performance model for the speedup of a generic RC system. We demonstrate how different parameters of speedup model can affect the performance of reconfigurable system (RS). In addition, we implement our pre-developed speedup model for a system that permits preloading functional blocks (FB) into the reconfigurable hardware (RH). The redevelopment of speedup model with the consideration of preloading demonstrates some interesting results that can be used to improve the performance of RH with a coprocessor. Our experiments show that the minimum and the maximum speedup mainly depend on the probabilities of miss and hit for the FB resides in the RH of coprocessor.